FTF=0, PDB=0, LPUART0=0, PIT=0, FTM0=0, ADC0=0, CRC=0, SPI0=0, DMAMUX=0, SPI1=0, DAC0=0, FTM2=0, FTM1=0, ADC1=0
System Clock Gating Control Register 6
| FTF | Flash Memory Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| DMAMUX | DMA Mux Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| ADC1 | ADC1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| LPUART0 | LPUART0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| SPI0 | SPI0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| SPI1 | SPI1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| CRC | CRC Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PDB | PDB Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PIT | PIT Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| FTM0 | FTM0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| FTM1 | FTM1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| FTM2 | FTM2 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| ADC0 | ADC0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| DAC0 | DAC0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |